Memory cell arrays comprising NROM memory cells (planar SONOS memory cells that can be programmed by channel hot electrons and can be erased by hot holes, as disclosed in U.S. Pat. No. 5,768,192, U.S. Pat. No. 6,011,725, and PCT Publication WO 99/60631) can be miniaturized more extensively by the memory cells not being arranged in a plane one beside the other, but rather at the walls of trenches etched out at the top side of a semiconductor body. A multiplicity of such trenches run at a distance from and parallel to one another and thus form a kind of comb structure at the surface of the semiconductor body.
The channels of the memory transistors are arranged in vertical fashion at the trench walls. The source and drain regions are arranged at the top side of the semiconductor body in a manner adjoining the trenches and in the trench bottoms. The source/drain regions are connected to bit lines. The gate electrodes of the memory transistors are arranged in the trenches and connected to word lines arranged transversely with respect to the bit lines on the top side of the memory cell array.
The word lines run transversely with respect to the direction of the trenches and therefore have to be electrically insulated from the source and drain regions in the semiconductor material. A thin gate dielectric has to be provided at the trench walls, while a thicker electrically insulating layer has to be provided on the top side of the source and drain regions in order to achieve a sufficient electrical insulation between the word lines and the source and drain regions with a low degree of capacitive coupling.
The gate dielectric is formed by a storage layer sequence, for which an oxide-nitride-oxide layer sequence is usually used, at the walls of the trenches. In this case, the nitride layer is provided as the actual storage layer in which, during the programming of the cell, electrons are trapped between the boundary layers made of oxide (trapping).
The problem that has arisen hitherto is that, in the case of simultaneous fabrication of the lower boundary layer made of oxide and the electrically insulating layer—preferably likewise formed from oxide—on the top sides of the source and drain regions, an oxide growth of uniform thickness forms either a gate dielectric layer that is too thick or an insulation layer that is too thin. An optimum tunnel oxide thickness is about 6 nm, which is too small for the insulation layer on the source and drain regions. For quality reasons, a deposited oxide is suitable as lower boundary layer (tunnel oxide) of the storage layer sequence only to a limited extent.